1. Field of the Invention
The present invention relates to a non-volatile memory (NVM) cell and a manufacturing method thereof, and more particularly, to an erasable NVM cell and a manufacturing method thereof.
2. Description of the Prior Art
An NVM is a common device for storing data in an integrated circuit, with one of its important characteristics being that the data stored in the NVM will not disappear after power is turned off. Generally speaking, hard disk drives, erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), and flash memory can be classified as NVM because data stored in these devices is not lost when power is turned off.
According to the limitation in programming capability, NVM can be divided into multi-time programmable (MTP) memory and one-time programmable (OTP) memory. MTP memory, such as EEPROM or flash memory, is repeatedly programmable to update data, and has specific circuits for erasing, programming, and reading operations. Unlike MTP memory, OTP memory is one-time programmable and has circuits for programming and reading operations without an erasing circuit, so the circuit for controlling the operations of the OTP memory is simpler than the circuit for controlling the operations of the MTP memory. In fact, in order to expand the practical applications of the OTP memory, an erasing method used in EPROM (ultraviolet illumination) is attempted to erase data stored in OTP memory. In addition, a simple circuit is designed to control OTP memory and simulate updateable ability like MTP memory.
Either an MTP memory cell or an OTP memory cell has a stacked structure, which is composed of a floating gate for storing electric charges, a control gate for controlling the charging of the floating gate, and an insulating layer (such as an ONO composite layer composed of an oxide layer, a silicon nitride layer, and an silicon oxide layer) positioned between the floating gate and the control gate. Like a capacitor, the memory cell stores electric charges in the floating gate to get a different threshold voltage Vth from the memory cell stores no electric charges in the floating gate, thus storing binary data such as 0 or 1.
Referring to the FIG. 1, FIG. 1 is a cross-sectional diagram of an NVM cell according to the prior art. As shown in FIG. 1, an NVM cell includes a substrate 10, a P-well 12 positioned in the substrate 10, a stacked structure, which is composed of an insulating layer 14, a floating gate 16, an insulating layer 18 and a control gate 20, positioned on the P-well 12, and an N-type doping region 22 positioned in the P-well 12 to surround the stacked structure. The floating gate 16 and the control gate 20 are normally formed of doped polysilicon. The insulating layer 14 positioned beneath the floating gate 16 is functioned as a tunneling oxide layer. The insulating layer 18 positioned between the floating gate 16 and the control gate 20 is an ONO composite layer. In addition, the N-type doping region 22 surrounding the floating gate 16 is functioned as a drain and a source to control the operation of programming, erasing or reading the NVM cell.
U.S. Pat. No. 6,207,507 B1 discloses a multi-level NVM cell to provide higher density memories. Please refer to FIG. 2 of a cross-sectional diagram of a multi-level NVM cell according to the prior art. As shown in FIG. 2, a multi-level NVM cell includes a substrate 30, a P-well 32 positioned in the substrate 30, an insulating layer 34 and an insulating layer 38 positioned on the P-well 32 to insulate three adjacent floating gates 36a, 36b, and 36c from one another. In addition, the multi-level NVM cell further includes an N-type doping region 40, functioning as a source and a drain, positioned in the P-well 32 and on either side of the floating gates 36b and 36c. An insulating layer 42 is formed to cover the three floating gates 36a, 36b, and 36c, and cover the N-type doping region 40. A control gate 44 is formed on the insulating layer 42. Since the multi-level NVM cell has three floating gates 36a, 36b, and 36c, it is capable of storing a 2-bit binary signal, such as 00, 01, 10 or 11.
Normally, the NVM cell uses Fowler Nordheim tunneling technique to erase data from the floating gate. During the operation of erasing the NVM cell, an electric field of the tunneling oxide layer (such as the insulating layer 14 shown in FIG. 1 or the insulating layers 34, 38 shown in FIG. 2) must be at least 10 million volts per centimeter (MV/cm). In order to prevent a high voltage from destructing the elements, the thickness of the tunneling oxide layer is decreased to between 80 and 120 angstroms (Å) to achieve the high electric field. Because of the limitation in the thickness of the tunneling oxide layer and the doping conditions, the manufacturing process of the conventional NVM cell is currently integrated with the manufacturing process of LV MOS transistors (with a gate oxide layer of 70 Å) and is not compatible with that of other higher operation voltage MOS transistors.